Event at a Glance
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The principal goal of DVClub Europe is to have fun while helping build the verification community through regular educational and networking events. DVClub Europe 2015 attendance is free and is open to all non-service provider semiconductor professionals.
Agenda (GMT):
Time | Session Description |
11.30 GMT | Arrival and Networking |
12.00 GMT | Welcome and Introduction Mike Bartley, Senior Vice President – VLSI Design, Tessolve |
12.05 GMT | Unifying Coverage Closure When Using Different Verification Techniques – Infineon Technologies UK Ltd, Darren Galpin (System IP Verification Manager) |
12.25 GMT | Bring IP Verification Closure to SoC, Scalable Methods to Bridge the Gap between IP and SoC Verification – Freescale Semiconductor Inc. Gaurav Gupta (Staff Design Engineer) |
12.45 GMT | System-Level Coverage Closure with Graph-Based Portable Stimulus Breker Verification Systems, Tom Anderson (VP Marketing) |
13.05 GMT | Reaching Coverage Should Be Science Not Art Synopsys, Adiel Khan (Senior Staff Engineer, Verification Group Business Unit.) |
13.25 GMT | Close and Networking |
Venues
- Bristol: Broadcom, 910 Aztec West, Almondsbury, Bristol, BS32 4SR
- Cambridge: ARM, 110 Fulbourn Road, Cambridge, CB1 9NJ
- Grenoble: STMicroelectronics – Polygone Scientifique, 12 Rue Jules Horowitz, Grenoble
- Sophia: Business Pôle, Entrée A, 1047, Route des Dolines, 06901 Sophia Antipolis Cedex
- Remote Access
Sponsors
DVCLUB Europe is made possible through the generosity of our sponsors.