System Integration

Implementing cost-effective system integration

solutions that are fully tested, proven and secure

With ever-increasing functionality being packed into every new product iteration, system integration has become a complex, time-consuming and error prone exercise.

The challenges posed in designing, integrating and testing a fully functional system comprising many IP blocks, modules and devices from a variety of different suppliers, without slipping the go-to-market window, has made system integration a truly formidable task beyond the reach of many engineering and product teams where resources are often limited.

Meeting the Challenges

To meet these system integration challenges tessolve deliver completely fully integrated solutions by leveraging our core expertise in the areas of testing, design, security, networking, and storage systems. Allowing for a more efficient integration of resources and offering the support you need to quickly implement fully tested, proven and cost-effective solutions.

Proven System Integration Competencies

Proven enterprise end-to-end application integration capabilities and skills across key industry verticals from supply chain management to insurance services
Flexible commercial models for service-aligned and result-based contracts
Business application consulting capabilities based on proven domain experience and technology expertise

Global presence and partnerships for transforming ideas into proven solutions
Fully tested and secure solutions based on tessolve best-in-class test strategies

Service Offerings

Enterprise architecture and application integration

Cloud enablement and security

Complete testing of the provided solution

Turnkey Services

Integration and testing services

Maintenance & Support services

Managed Services

Supported Industry verticals

Industrial
Consumer Electronics
Automotive
Retail
Medical

Customer Success Stories

Helped a taxi fleet operator reduce operational costs by 25% by architecting, designing and deploying a cloud-based system with GPS tracking, live control room monitoring and ability to generate on-the-fly intelligence reports
Enabled live inventory tracking for a shopping retailer with multiple stores across the country

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ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

An Emulation Strategy for Artificial Intelligence Designs

The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

3 Key Points:

Deterministic solution for AI chips verification

Full virtual solution for HW/SW verification

TERAOPS/Watt assessement prior silicon availability

Name: Mike Bartley

Designation: Senior Vice President – VLSI Design

Title: Introduction

Biography:

Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.

System Integration

Implementing cost-effective system integration

solutions that are fully tested, proven and secure

Meeting the Challenges

Proven System Integration Competencies